Integrated semiconductor circuit configuration having stabilized conductor tracks

ABSTRACT

An integrated semiconductor circuit configuration includes stabilized conductor tracks which run in different planes. Critical locations of the conductor tracks which are dictated by the layout are provided with dummy contacts.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to an integrated semiconductor circuitconfiguration having conductor tracks or interconnects that run in atleast two different planes, in which conductor tracks in at least one ofthe planes are provided in close proximity and essentially parallel toone another.

During the fabrication of integrated semiconductor circuitconfigurations, such as semiconductor memories for example, if, by wayof example, conductor tracks run closely adjacent and parallel to oneanother and one of those conductor tracks is interrupted, it is possiblefor so-called proximity effects to occur. Those effects ultimatelyresult in a conductor track exhibiting a critical location in such aregion, at which the conductor track can become unstable and even tendtoward an interruption. That instability is explained below withreference to FIG. 4. FIG. 3 shows how a discontinuity affects aconductor track.

If such discontinuities are present on both sides of a conductor track,then such a conductor track may become constable, and it may even break.

Such critical locations of conductor tracks need not necessarily be dueonly to so-called proximity effects. Conductor tracks can also be guidedin certain ways, having to do especially with curvatures having a smallradius of curvature, that can lead to such critical locations.

It goes without saying that such critical locations are highlyundesirable, which is why the geometrical dimensions of the conductortracks are often enlarged at those locations. However, such a procedurehas the disadvantage of causing the conductor tracks and the spacingsbetween them to thus inevitably be enlarged, which is at odds with theconstant striving to miniaturize integrated semiconductor circuitconfigurations.

SUMMARY OF THE INVENTION

It is accordingly an object of the invention to provide an integratedsemiconductor circuit configuration having stabilized conductor tracks,which overcomes the hereinafore-mentioned disadvantages of theheretofore-known devices of this general type and in which instabilitiesof conductor tracks at critical locations can be reliably avoided.

With the foregoing and other objects in view there is provided, inaccordance with the invention, an integrated semiconductor circuitconfiguration, comprising conductor tracks having a given layout andrunning in at least two different planes, the conductor tracks in atleast one of the planes disposed in close proximity and substantiallyparallel to one another, and the conductor tracks having a dummy contactdisposed underneath the conductor tracks at critical locations dictatedby the given layout.

The integrated semiconductor circuit configuration according to theinvention thus provides a surprisingly simple solution to the aboveproblem of critical locations especially due to the proximity effect. Atsuch locations, the conductor tracks have a dummy contact situatedunderneath them in a simple manner. The dummy contact can lead as far asan underlying metalization plane without establishing an electricalconnection there. As a result, the conductor track has a sufficientcross section in the region of the critical location, so that anyinstability of the conductor track and any interruption thereof arereliably prevented.

In accordance with another feature of the invention, the dummy contactsare provided at critical locations which are dictated by an interruptionof one of two closely adjacent, parallel conductor tracks.

In accordance with a concomitant feature of the invention, the conductortracks have a width of approximately 150 to 250 nm and a spacing fromone another on the order of magnitude of approximately 130 to 180 nm.

Therefore, in the case of the integrated semiconductor circuitconfiguration according to the invention, dummy contacts are provided atcritical locations of conductor tracks. These dummy contacts increasethe cross sections of the conductor track at these critical locations,with the result that it is no longer possible for instabilities of theconductor track to occur or even for the latter to break. Increasedelectromigration susceptibilities are reliably avoided.

The use of the dummy contacts thus makes it possible to provide layoutshaving critical geometries, that is to say particularly smallstructures, with the result that the invention promotes furtherminiaturization of integrated semiconductor circuit configurations.

The present invention affords advantages in a particularly advantageousmanner in so-called damascene and dual damascene metalization systems ofintegrated circuits, since in these systems, the dummy contacts resultnot only in a local widening of the geometry of the conductor track butalso in a local increase in the line cross section.

If appropriate, the invention can also be used in an advantageous mannerin other lithographically defined metalization systems, and not just forintegrated circuits.

Other features which are considered as characteristic for the inventionare set forth in the appended claims.

Although the invention is illustrated and described herein as beingembodied in an integrated semiconductor circuit configuration havingstabilized conductor tracks, it is nevertheless not intended to belimited to the illustrated details, since various modifications andstructural changes may be made therein without departing from the spiritof the invention and within the scope and range of equivalents of theclaims.

The construction and method of operation of the invention, however,together with additional objects and advantages thereof will be bestunderstood from the following description of specific embodiments whenread in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagrammatic plan view of various conductor tracks withdummy contacts according to the present invention;

FIG. 2 is a fragmentary, sectional view through a conductor track with adummy contact according to the invention;

FIG. 3 is a fragmentary, sectional view taken along a line A-A′ in FIG.4 through an existing conductor track; and

FIG. 4 is a plan view of conductor tracks, which is used to explain theproblem underlying the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now in detail to the figures of the drawings, in whichmutually corresponding components are provided with the same referencesymbols, and first, particularly, to FIG. 4 thereof, there is seen aplan view of three conductor tracks or interconnects 1 to 3, wherein theconductor track 2 is interrupted in its center. This interruption may becaused, for example, by the fact that opposite central ends of thisconductor track 2 in FIG. 4 are connected through contacts to acomponent located in a different metallization plane. At any rate, thisinterruption of the conductor track 2 means that there is adiscontinuity in the proximity of the conductor tracks 1 and 3. Suchdiscontinuities occur, in particular, whenever two mutually adjacentconductor tracks cross one another in a twist region, for example in asemiconductor memory. Further conductor tracks adjoining this twistregion then “see” the discontinuity of the twist region.

At any rate, it has been shown that adjacent conductor tracks areadversely affected by such discontinuities. This is because if adiscontinuity is present, then during fabrication, the adjacentconductor tracks, that is to say the conductor tracks 1 and 3 in thepresent example, may have a reduced cross section in the region of thediscontinuity, as is indicated by dashed lines 4 for the respectiveconductor tracks 1 and 3.

FIG. 3 is a cross-sectional view taken along a line A′A′ in FIG. 4,showing how this discontinuity affects the conductor track 1. Theconductor track 1, which runs, for example, on an insulating layer 5made of silicon dioxide, has a reduced cross section in the region ofthe discontinuity of the conductor track 2. That cross section isdelimited by the dashed line 4.

FIG. 1 is a plan view of a metalization plane which shows conductortracks or interconnections 10 to 15. On one hand, the conductor tracks10, 11 as well as 14, 15 each cross one another in a twist region. Inother words, the conductor track 10 is guided over the conductor track11, in a further plane located above the metalization plane of FIG. 1,at a distance, and is isolated by an insulating layer. The conductortracks 12 and 13, on the other hand, are continuous conductor tracks.

The conductor tracks 14 and 15 have a similar structure to the conductortracks 10 and 11.

These conductor tracks 10 to 15 may, for example, be bit lines of amemory cell array. The width of the conductor tracks lies between 150and 250 nm and is preferably approximately 200 nm. The spacing betweenthe conductor tracks lies between 130 and 180 nm. The conductor tracksthemselves may be composed of aluminum or copper or other suitablematerials.

It has been shown that during the metalization of the conductor tracks10 to 15, critical locations are produced, due to the proximity effect,wherever discontinuities are present in the vicinity of the conductortracks. Such discontinuities occur when an adjacent conductor track isinterrupted. The conductor tracks have instabilities, which can evenlead to the conductor tracks breaking, at these discontinuous locations.

According to the invention, dummy contacts 16 to 20 are provided atthese critical locations. The dummy contacts lead to a plane locatedbelow the conductor track plane of FIG. 1.

FIG. 2 shows a section through such a dummy contact, for example thedummy contact 17. The conductor track 11 has a reduced cross section inthis case due to the discontinuous proximity. As is shown in FIG. 2, thereduced cross section can also occur on both sides, if appropriate. Thedummy contact 17 is therefore provided underneath the conductor track 11in order to strengthen the latter. The dummy contact 17 penetratesthrough an insulating layer 5 made of silicon dioxide and leads as faras a deeper conductor track plane 21. Additional conductor tracks 22,which lie on a silicon dioxide layer 23 and are electrically insulatedfrom the dummy contact 17, may run on this conductor track plane 21.

What is essential to the present invention, then, is that conductortracks are deliberately provided with dummy contacts at criticallocations, with the result that any instability of the conductor trackand/or breaking thereof can be reliably avoided. These dummy contactsneed not, of course, extend as far as the next conductor track plane.Rather, it suffices for the dummy contacts to have a cross section suchthat any instability and/or breaking of the conductor track which theystrengthen can be reliably precluded.

We claim:
 1. An integrated semiconductor circuit configuration, comprising: conductor tracks running in at least two different planes, said conductor tracks in at least one of said planes disposed in close proximity and substantially parallel to one another, and said conductor tracks having a dummy contact disposed underneath said conductor tracks at locations affected by a discontinuity.
 2. The integrated semiconductor circuit configuration according to claim 1, wherein said discontinuity is generated by an interruption of one of two closely adjacent, parallel conductor tracks.
 3. The integrated semiconductor circuit configuration according to claim 1, wherein said conductor tracks have a width of 150 to 250 nm.
 4. The integrated semiconductor circuit configuration according to claim 1, wherein said conductor tracks have a width of 200 nm.
 5. The integrated semiconductor circuit configuration according to claim 1, wherein said conductor tracks are separated by a spacing of between 130 and 180 nm.
 6. The integrated semiconductor circuit configuration according to claim 1, wherein said conductor tracks are formed of a material selected from the group consisting of aluminum and copper.
 7. The integrated semiconductor circuit configuration according to claim 1, wherein said discontinuity is in a twist region and caused by a twist.
 8. The integrated semiconductor circuit configuration according to claim 1, wherein said discontinuity is caused by another conductor track. 